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IIS2DLPC 数据表(PDF) 56 Page - STMicroelectronics |
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IIS2DLPC 数据表(HTML) 56 Page - STMicroelectronics |
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56 / 69 page ![]() Register description IIS2DLPC 56/69 DocID031788 Rev 4 8.17 OUT_Z_H (2Dh) Z-axis MSB output register (r). Table 55. OUT_Z_H register The 8 most significant bits of linear acceleration sensor Z-axis output. Together with the OUT_Z_L (2Ch) register, it forms the output value expressed as a 16-bit word in 2's complement. 8.18 FIFO_CTRL (2Eh) FIFO control register (r/w). Table 56. FIFO_CTRL register Table 57. FIFO_CTRL register description Z_H7 Z_H6 Z_H5 Z_H4 Z_H3 Z_H2 Z_H1 Z_H0 FMode2 FMode1 FMode0 FTH4 FTH3 FTH2 FTH1 FTH0 FMode[2:0] FIFO mode selection bits. Default: 000. For further details refer to Table 58 FTH[4:0] FIFO threshold level setting. Table 58. FIFO mode selection FMode[2:0] Mode description 000 Bypass mode: FIFO turned off 001 FIFO mode: Stops collecting data when FIFO is full. 010 Reserved 011 Continuous-to-FIFO: Stream mode until trigger is deasserted, then FIFO mode 100 Bypass-to-Continuous: Bypass mode until trigger is deasserted, then FIFO mode 101 Reserved 110 Continuous mode: If the FIFO is full, the new sample overwrites the older sample. 111 Reserved |
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