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IIS2DLPC 数据表(PDF) 40 Page - STMicroelectronics

部件名 IIS2DLPC
功能描述  MEMS digital output motion sensor: high-performance ultra-low-power 3-axis accelerometer for industrial applications
PDF  69 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

IIS2DLPC 数据表(HTML) 40 Page - STMicroelectronics

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Digital interfaces
IIS2DLPC
40/69
DocID031788 Rev 4
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL low to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left high by
the slave. The master can then abort the transfer. A low-to-high transition on the SDA line
while the SCL line is high is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
Table 18. Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
SAK
SAK
Table 19. Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
DATA
DATA
SP
Slave
SAK
SAK
SAK
SAK
Table 20. Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
SAK
SAK
DATA
Table 21. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
SUB
SR SAD+R
MAK
MAK
NMAK SP
Slave
SAK
SAK
SAK
DATA
DATA
DATA



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