MPF5024AMBA0ES datasheet(21/93 Pages) NXP

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NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

21 / 93

• Tj < thermal shutdown threshold

• TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

14.5.2 Power up sequencing

The power up sequencer controls the time and order in which the voltage regulators and

other controlling I/O are enabled when going from the Off mode into the run state.

The OTP_SEQ_TBASE[1:0] bits set the default time base for the power up and power

down sequencer.

The SEQ_TBASE[1:0] bits can be modified during the system On state in order to

change the sequencer timing during run/standby transitions as well as the power down

sequence.

Table 17. Power up time base register

OTP bits

OTP_SEQ_TBASE[1:0]

Functional bits

SEQ_TBASE[1:0]

Sequencer time base

(µs)

120

250

500

The power up sequence may include any of the following:

• Switching regulators

• PGOOD pin if programmed as a GPO

• RESETBMCU

The default sequence slot for each one of these signals is programmed via the OTP

configuration registers. They can be modified in the functional I2C register map to change

the order in which the sequencer behaves during the run/standby transitions as well as

the power down sequence.

The x_SEQ[7:0] bits set the regulator/pin sequence from 0 to 254. Sequence code 0x00

indicates that the particular output is not part of the startup sequence and remains in OFF

(in case of a regulator) or remains low/disabled (in case PGOOD pin used as a GPO).

Table 18. Power up sequence registers

OTP bits

OTP_SWx_SEQ[7:0]/

OTP_PGOOD_SEQ[7:0]/

OTP_RESETBMCU_SEQ[7:0]

Functional bits

SWx_SEQ[7:0]/

PGOOD_SEQ[7:0]/

RESETBMCU_SEQ[7:0]

Sequence slot

Startup time

(µs)

00000000

Off

00000001

SLOT0

(right after PWRON event is

valid)

00000010

SEQ_TBASE x SLOT1

11111111

254

SEQ_TBASE x SLOT254

If RESETBMCU is not programmed in the OTP sequence, it will be enabled by default

after the last regulator programmed in the power up sequence.

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