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MPF5024AMBA0ES 数据表(PDF) 32 Page - NXP Semiconductors |
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MPF5024AMBA0ES 数据表(HTML) 32 Page - NXP Semiconductors |
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32 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 32 / 93 aaa-030051 RESETBMCU PGOOD4 PGOOD3 PGOOD2 SYSTEM ON SW4 SW3 SW2 PGOOD1 SW1 PGOOD (optional) Figure 14. Correct power up (no fault during power up) If any of the regulators are powered up before RESETBMCU is out of regulator, RESETBMCU is not de-asserted and the power up sequence is stopped for up to 2.0 ms. If the fault is cleared and all internal PG signals are asserted within the 2.0 ms timer, RESETBMCU is de-asserted and the power up sequence continues where it stopped as shown in Figure 15. |
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