MPF5024AMBA0ES datasheet(45/93 Pages) NXP

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NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

45 / 93

14.9.11 SDA and SCL (I2C bus)

Communication with the PF5024 is done through I2C and it supports high-speed

operation mode with up to 3.4 MHz operation. SDA and SCL are pulled up to VDDIO with

1.5 kΩ resistors.

The PF5024 is designed to operate as a slave device during I2C communication. The

default I2C device address is set by the OTP_I2C_ADD[2:0].

Table 33. I2C address configuration

OTP_I2C_ADD[2:0]

Device address

000

0x08

001

0x09

010

0x0A

011

0x0B

100

0x0C

101

0x0D

110

0x0E

111

0x0F

See http://www.nxp.com/documents/user_manual/UM10204.pdf for detailed information

on the digital I2C communication protocol implementation.

During an I2C transaction, the communication will latch after the 8th bit sent. If the data

sent is not a multiple of 8 bit, any word with less than 8 bits will be ignored. If only 7 bits

are sent, no data is written and the logic will not provide an ACK bit to the MCU.

From an IC level, a wrong I2C command can create a system level safety issue. For

example, though the MCU may have intended to set a given regulator’s output to 1.0 V, it

may be erroneously registered as 1.1 V due to noise in the bus.

To prevent a wrong I2C configuration, various protective mechanisms are implemented.

14.9.11.1 I2C CRC verification

When this feature is enabled, a selectable CRC verification is performed on each I2C

transaction.

• When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.

• When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled.

After each I2C transaction, the device calculates the corresponding CRC byte to ensure

the configuration command has not been corrupted.

When a CRC fault is detected, the PF5024 ignores the erroneous configuration

command and triggers a CRC_I interrupt asserting the INTB pin, provided the interrupt is

not masked.

The PF5024 implements a CRC-8-SAE, per the SAE J1850 specification.

• Polynomial = 0x11D

• Initial value = 0xFF

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