MPF5024AMBA0ES datasheet(39/93 Pages) NXP

39 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

39 / 93

STANDBY (pin)

STANDBYINV (I2C bit)

STANDBY control

Not in Standby mode

14.9.3 RESETBMCU

RESETBMCU is an open-drain, active low output used to bring the processor (and

peripherals) in and out of reset.

The time slot RESETBMCU is de-asserted during the power up sequence is programmed

by the OTP_RESETBMCU_SEQ[7:0] bits, and it is a condition to enter the system On

state.

During the system On state, the RESETBMCU is de-asserted (pulled high), and it is

asserted (pulled low) as indicated in the power down sequence, when a system power

down or reset is initiated.

In the application, RESETBMCU can be pulled up to VDDIO by a 10 kΩ external resistor.

It is also recommended to add a 10 nF bypass capacitor close to the pin to improve the

EM immunity performance.

14.9.4 INTB

INTB is an open-drain, active low output. This pin is asserted (pulled low) when any

interrupt occurs, provided that the interrupt is not masked.

INTB is de-asserted after the corresponding interrupt latch is cleared by software, which

requires writing a “1” to the interrupt bit.

An INTB_TEST bit is provided to allow a manual test of the INTB pin. When INTB_TEST

is set to 1, the interrupt pin asserts for 100 µs and then de-asserts to its normal state.

The INTB_TEST bit self-clears to 0 automatically after the test pulse is generated.

In the application, INTB can be pulled up to VDDIO with an external 100 kΩ resistor.

14.9.5 WDI

WDI is an input pin to the PF5024 and is intended to operate as an external watchdog

monitor.

When the WDI pin is connected to the watchdog output of the processor, this pin is used

to detect a pulse to indicate a watchdog event is requested by the processor. When the

WDI pin is asserted, the device starts a watchdog event to place the PMIC outputs in a

default known state.

The WDI pin is monitored during the system On state. In the Off modes and during the

power up sequence, the WDI pin is masked until RESETBMCU is de-asserted.

The WDI can be configured to assert on the rising or the falling edge using the

OTP_WDI_INV bit.

• When OTP_WDI_INV = 0, the device starts a WD event on the falling edge of the WDI.

• When OTP_WDI_INV = 1, the device starts a WD event on the rising edge of the WDI.

A 10 µs debounce filter is implemented on either rising or falling edge detection to

prevent false WDI signals to start a watchdog event.

The WDI_MODE bit allows the WDI pin to react in two different ways:

• When WDI_MODE = 1, a WDI asserted performs a hard WD reset.

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