MPF5024AMBA0ES datasheet(13/93 Pages) NXP

13 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

13 / 93

• A CRC is performed on the mirror registers during the self-test routine, to ensure the

integrity of the registers before powering up

• ABIST test on all voltage monitors.

To allow for varying settling times for the internal bandgap and clocks, the self-test block

is executed up to three times (with 2.0 ms between each test) if a failure is encountered,

the state machine proceeds to the fail-safe transition.

A failure in the ABIST test is not interpreted as a self-test failure and it only sets the

corresponding ABIST flag for system information. The MCU is responsible for reading the

information and deciding whether it can continue with a safe operation. See Section 18.1

"System safety strategy" for the functional safety strategy of PF5024.

Upon a successful self-test, the state machine proceeds to the QPU_Off state.

13.1.4 QPU_Off state

The QPU_Off state is a higher power consumption Off mode, in which all internal circuitry

required for a power on is biased and ready to start a power up sequence.

If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state,

and waits until a valid turn on event is present.

In this state, if VDDIO supply is provided externally, the device is able to communicate

through I2C to access and modify the mirror registers in order to operate the device in

TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and

hardwire default configurations".

If a power up event is started and any of the TRIM_NOK, OTP_NOK or STEST_NOK

flags are asserted, the device ignores the power up event and remains in the QPU_Off

state. See Section 17 "OTP/TBB and hardwire default configurations" for debugging a

fuse loading failure.

Upon a power up event, the default configuration from OTP or hardwire is loaded into

their corresponding I2C functional register in the transition from QPU_Off to power up

state.

13.1.5 Power up sequence

During the power up sequence, the external regulators are turned on in a predefined

order as programmed by the default (OTP or hardwire) sequence.

The RESETBMCU is also programmed as part of the power up sequence, and it is used

as the condition to enter the system On state. The RESETBMCU may be released in the

middle of the power up sequence, in this case, the remaining supplies in the power up

continues to power up as the device is in the run state. See Section 14.5.2 "Power up

sequencing" for details.

13.1.6 System On state

During the system On state, the MCU is powered and out of reset and the system is fully

operational.

The system On is a virtual state composed by two modes of operations:

• Run state

• Standby state

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