PCF8536AT datasheet(26/54 Pages) NXP

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PCA85233

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Product data sheet

Rev. 5 — 12 November 2018

26 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

8.5 I2C-bus controller

The PCA85233 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCA85233 are

the acknowledge signals from the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data, and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally tied

to VSS which defines the hardware subaddress 0. In multiple device applications A0

and A1 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a

common I2C-bus slave address have the same hardware subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA85233. The entire I2C-bus slave address byte is shown in Table 17.

The PCA85233 is a write-only device and will not respond to a read access, therefore bit 0

should always be logic 0. Bit 1 of the slave address byte that a PCA85233 will respond to,

is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).

Fig 17. Acknowledgement on the I2C-bus

Table 17.

I2C slave address byte

Slave address

Bit

MSB

LSB

SA0

R/W

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