PCF8536AT datasheet(7/54 Pages) NXP

7 / 54 page

PCA85233

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Product data sheet

Rev. 5 — 12 November 2018

7 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

or equals an external clock frequency fclk(ext):

(2)

7.2.1.1

Internal clock

The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output

from pin CLK provides the clock signal for any cascaded PCA85233 in the system.

7.2.1.2

External clock

Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the

external clock input.

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.2.2 Frame frequency

The clock frequency fclk determines the LCD frame frequency ffr and is calculated as

follows:

(3)

The internal clock frequency fclk can be selected using pin FF. As a result 2 frame

frequencies are available: 150 Hz or 220 Hz (typical), see Table 11.

[1]

FF has no effect when an external clock is used but must not be left floating.

The timing of the PCA85233 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between all the PCA85233 in the system.

7.2.3 Blinking

The display blink capabilities of the PCA85233 are very versatile. The whole display can

blink at frequencies selected by the blink-select command (see Table 10). The blink

frequencies are derived from the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode selected (see Table 12).

clk

clk ext



Table 11.

LCD frame frequencies

Pin FF tied to[1]

Typical clock frequency (Hz)

LCD frame frequency (Hz)

VDD

3600

150

VSS

5280

220

clk

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