PCF8536AT datasheet(12/54 Pages) NXP

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PCA85233

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Product data sheet

Rev. 5 — 12 November 2018

12 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 14.

In the case described in Table 14 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to segments/elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written.

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6.

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6.

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some segments/elements remain unused or can be used, but it has to be considered in

the module layout process as well as in the driver software design.

7.3.4 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to

fill the RAM over the RAM address boundary. If the PCA85233 is part of a cascade the

additional bits fall into the next device that also generates the acknowledge signal. If the

PCA85233 is a single device or the last device in a cascade the additional bits will be

discarded and no acknowledge signal will be generated.

7.3.5 Output bank selector

The output bank selector (see Table 9) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

selected LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The PCA85233 includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex

Table 14.

Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

a1/b7 b4

b1/c7 c4

c1/d7 d4

d1/e7 e4

a0/b6 b3

b0/c6 c3

c0/d6 d3

d0/e6 e3

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