TMS320F28069MPZPQ datasheet(80/181 Pages) TI

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INT12

MUX

INT11

INT2

INT1

CPU

(Enable)

(Flag)

INTx

INTx.8

PIEIERx[8:1]

PIEIFRx[8:1]

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals

External

Interrupts

(Enable)

(Flag)

IER[12:1]

IFR[12:1]

Global

Enable

INTM

PIEACKx

(Enable/Flag)

TMS320F28069, TMS320F28069F, TMS320F28069M, TMS320F28068F, TMS320F28068M

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064

TMS320F28063, TMS320F28062, TMS320F28062F

SPRS698H – NOVEMBER 2010 – REVISED MARCH 2020

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TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062

TMS320F28062F

Detailed Description

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with

8 interrupts per group equals 96 possible interrupts. Table 6-17 shows the interrupts used by 2806x

devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine (ISR)

corresponding to the vector specified. The TRAP #0 instruction attempts to transfer program control to the

address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector.

Therefore, the TRAP #0 instruction should not be used when the PIE is enabled. Doing so will result in

undefined behavior.

When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the ISR

corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction fetches the

vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.

Figure 6-17. Multiplexing of Interrupts Using the PIE Block

TMS320F28069MPZPQ 数据表(PDF) 80 Page - Texas Instruments

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