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TMS320F28069MPZPQ 数据表(PDF) 21 Page - Texas Instruments

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部件名 TMS320F28069MPZPQ
功能描述  TMS320F2806x Microcontrollers
PDF  181 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320F28069MPZPQ 数据表(HTML) 21 Page - Texas Instruments

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TMS320F28069, TMS320F28069F, TMS320F28069M, TMS320F28068F, TMS320F28068M
TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064
TMS320F28063, TMS320F28062, TMS320F28062F
www.ti.com
SPRS698H – NOVEMBER 2010 – REVISED MARCH 2020
Submit Documentation Feedback
Product Folder Links: TMS320F28069 TMS320F28069F TMS320F28069M TMS320F28068F TMS320F28068M
TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28062F
Specifications
Copyright © 2010–2020, Texas Instruments Incorporated
Table 4-1. Signal Descriptions(1) (continued)
PIN NAME
PIN NO.
I/O/Z
DESCRIPTION
PZ
PZP
PN
PFP
GPIO53
65
–
I/O/Z
General-purpose input/output 53
EQEP1I
I/O
Enhanced QEP1 index
MFSXA
I/O
McBSP transmit frame synch
Reserved
–
Reserved
GPIO54
69
–
I/O/Z
General-purpose input/output 54
SPISIMOA
I/O
SPI-A slave in, master out
EQEP2A
I
Enhanced QEP2 input A
HRCAP1
I
High-Resolution Input Capture 1
GPIO55
75
–
I/O/Z
General-purpose input/output 55
SPISOMIA
I/O
SPI-A slave out, master in
EQEP2B
I
Enhanced QEP2 input B
HRCAP2
I
High-Resolution Input Capture 2
GPIO56
85
–
I/O/Z
General-purpose input/output 56
SPICLKA
I/O
SPI-A clock input/output
EQEP2I
I/O
Enhanced QEP2 index
HRCAP3
I
High-Resolution Input Capture 3
GPIO57
89
–
I/O/Z
General-purpose input/output 57
SPISTEA
I/O
SPI-A slave transmit enable input/output
EQEP2S
I/O
Enhanced QEP2 strobe
HRCAP4
I
High-Resolution Input Capture 4
GPIO58
94
–
I/O/Z
General-purpose input/output 58
MCLKRA
I/O
McBSP receive clock
SCITXDB
O
SCI-B transmit data
EPWM7A
O
Enhanced PWM7 output A and HRPWM channel
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain,
↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the
GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the
Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual.
(3) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more
information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Technical Reference Manual.



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