TMS320F28069MPZPQ datasheet(13/181 Pages) TI

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TMS320F28069, TMS320F28069F, TMS320F28069M, TMS320F28068F, TMS320F28068M

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SPRS698H – NOVEMBER 2010 – REVISED MARCH 2020

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Terminal Configuration and Functions

4.2

Signal Descriptions

Table 4-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate

functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs

are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup (PU), which can be selectively

enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the

PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins

do not have an internal pullup.

NOTE

When the on-chip voltage regulator (VREG) is used, the GPIO19, GPIO26–27, and

GPIO34–38 pins could glitch during power up. This potential glitch will finish before the boot

mode pins are read and will not affect boot behavior. If glitching is unacceptable in an

application, 1.8 V could be supplied externally. Alternatively, adding a current-limiting resistor

(for example, 470 Ω) in series with these pins and any external driver could be considered to

limit the potential for degradation to the pin and/or external circuitry. There is no power-

sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V

transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V

transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin

during power up. To avoid this behavior, power the VDD pins before or simultaneously with

the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach

0.7 V.

Table 4-1. Signal Descriptions(1)

PIN NAME

PIN NO.

I/O/Z

DESCRIPTION

PZP

PFP

JTAG

TRST

JTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan

system control of the operations of the device. If this signal is not connected or driven

low, the device operates in its functional mode, and the test reset signals are ignored.

NOTE: TRST is an active-high test pin and must be maintained low at all times during

normal device operation. An external pulldown resistor is required on this pin. The

value of this resistor should be based on drive strength of the debugger pods

applicable to the design. A 2.2-k

Ω resistor generally offers adequate protection.

Because this is application-specific, TI recommends validating each target board for

proper operation of the debugger and the application. (

↓)

TCK

See GPIO38

See GPIO38. JTAG test clock with internal pullup. (

↑)

TMS

See GPIO36

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control

input is clocked into the TAP controller on the rising edge of TCK. (

↑)

TDI

See GPIO35

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the

selected register (instruction or data) on a rising edge of TCK. (

↑)

TDO

See GPIO37

O/Z

See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected

(8-mA drive)

FLASH

VDD3VFL

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

TEST2

I/O

Test Pin. Reserved for TI. Must be left unconnected.

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