ES9028PRO datasheet(21/57 Pages) ESS

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July 6, 2020

CONFIDENTIAL INFORMATION v3.6

ES9028PRO 32-Bit HyperStream® II 8-Channel Audio DAC

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-

8800 • Fax (408) 643-8801

Bits

[7:4]

[3:0]

Mnemonic

gpio2_cfg

gpio1_cfg

Default

4’d8

Bits

[7:4]

[3:0]

Mnemonic

gpio4_cfg

gpio3_cfg

Default

4’d8

GPIO Table

The GPIO can each be configured in one of several ways.

The table below is for programming each independent GPIO configuration value.

gpioX_cfg Name

I/O

Direction

Details

4’d 0

Automute Status

Output

Output is high when an automute has been triggered. This signal is

analogous to the automute_status register (register 64).

4’d 1

Lock Status

Output

Output is high when lock is triggered. This signal is analogous to

the lock_status register (register 64).

4’d 2

Volume Min

Output

Output is high when all digital volume controls have been ramped to

minus full scale. This can occur, for example, if automute is enabled

and set to mute the volume.

4’d 3

CLK

Output

Output is a buffered MCLK signal which can be used to synchronize

other devices.

4’d 4

Automute/Lock Interrupt

Output

Output is high when the contents of register 64 have been modified

(meaning that the lock_status or automute_status register have

been changed). Reading register 64 will clear this interrupt.

4’d 5

ADC_CLK

Output

Output is a buffered ADC clock signal. The ADC clock signal is

defined by the adc_clk_sel register.

4’d6

Reserved

4’d 7

Output 1’b0

Output

Output is forced low

4’d 8

Standard Input

Input

Places the GPIO into a high impedance state, allowing the customer

to provide a digital signal and then read that signal back via the I2C

4’d 9

Input Select

Input

Places the GPIO into a high impedance state and allows the

customer to toggle the input selection between two modes using the

GPIO. See register 15 for more information.

4’d 10

Mute All

Input

Places the GPIO into a high impedance state and allows the

customer to force a mute condition by applying a logic high signal to

the GPIO. When a logic low signal is applied the DAC will exhibit

normal operation.

4’d11

Reserved

4’d12

Reserved

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