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ES9028PRO 数据表(PDF) 6 Page - ESS Technology,Inc

部件名 ES9028PRO
功能描述  32-Bit HyperStream짰 II 8-Channel Audio DAC
PDF  57 Pages
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制造商  ESS [ESS Technology,Inc]
网页  http://www.esstech.com
标志 ESS - ESS Technology,Inc

ES9028PRO 数据表(HTML) 6 Page - ESS Technology,Inc

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CONFIDENTIAL INFORMATION v3.6
July 6, 2020
ES9028PRO 32-Bit HyperStream® II 8-Channel Audio DAC
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-
8800 • Fax (408) 643-8801
6
System Clock and Audio Inputs
Sampling Rate Notations
Mode
FSR
raw sample rate at
audio interface
fs
sample rate for filter
specification
DSD
DATA_CLK
FSR / 64
DoP
Frame Clock Rate
FSR / 4
Serial (PCM) Normal Mode
Frame Clock Rate
FSR
Serial (PCM) OSF Bypass Mode
Frame Clock Rate
FSR / 8
SPDIF
SPDIF Audio Rate
FSR
System Clock (XIN) and Audio Master Clock (MCLK)
The system clock (XIN) can be generated with a crystal using the built-in oscillator or supplied externally.
o
The maximum XIN frequency is 100MHz as specified in ANALOG PERFORMANCE and XIN Timing.
o
The audio master clock (MCLK) is divided down from XIN via clock_gear in Register 0: System Registers.
o
The minimum MCLK frequency for a given raw sample rate FSR is specified in ANALOG PERFORMANCE.
o
The minimum MCLK frequency for a given I2C clock is specified in the table under I2C Timing Table.
PCM Pin Connections
Pin Name
Description
DATA1
Frame clock
DATA5~2
8-channel PCM serial data
DATA_CLK
Bit clock for PCM audio format
Note: DATA_CLK frequency must be (2 x serial_length) x FSR.
serial_length can be set in Register 2: Serial Data Configuration and Automute Enable
SPDIF Pin Connections
Pin Name
Description
GPIO4~1
SPDIF input 13~10
DATA8~1
SPDIF input 9~2
DATA_CLK
SPDIF input 1
An SPDIF source multiplexer allows for up to 13 SPDIF sources to be connected to the data and GPIO pins selectable via
Register 11: SPDIF Mux and GPIO Inversion. SPDIF input mode can be manually selected by input_select in Register 1:
Input selection or automatically selected if auto_select in Register 1: Input selection is set to a mode allowing automatic
SPDIF selection.
DSD Pin Connections
Pin Name
Description
DATA8~1
8-channel DSD data input
DATA_CLK
Bit clock for DSD data input
Note: DATA_CLK frequency must be FSR.



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