ES9028PRO datasheet(10/57 Pages) ESS

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CONFIDENTIAL INFORMATION v3.6

July 6, 2020

ES9028PRO 32-Bit HyperStream® II 8-Channel Audio DAC

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-

8800 • Fax (408) 643-8801

Time Domain Jitter Eliminator and DPLL

By default, the DAC works in Jitter Eliminator mode allowing the audio interface timing to be asynchronous to MCLK. A DPLL

constantly updates the FSR/MCLK ratio to calculate the true 32-bit timing of the incoming audio samples allowing the ESS

patented Time Domain Jitter Eliminator to remove any distortion caused by jitter.

•

The DPLL acquisition speed can be set by lock_speed in Register 10: Master Mode and Sync Configuration.

•

The PCM/SPDIF DPLL bandwidth can be set via dpll_bw_serial in Register 12: Jitter Eliminator / DPLL Bandwidth

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The DSD DPLL bandwidth can be set via dpll_bw_dsd in Register 12: Jitter Eliminator / DPLL Bandwidth

For best performance, the DPLL bandwidth should be set to the minimum setting that will keep the DPLL reliably in lock.

Sample Rate Calculation

The raw sample rate (FSR) can be calculated from Register 66-69 : DPLL Number using the following formula:

FSR =

(dpll_num ∗ MCLK)

232

Synchronous Mode (PCM mode only)

The DPLL can be bypassed if the incoming PCM audio is synchronous to MCLK with the relationship MCLK=128FSR. This

can be enabled via 128fs_mode in Register 10: Master Mode and Sync Configuration.

DAC Full-Scale Gain Calibration

DAC gain calibration enables uniform output level across multiple chips by compensating for chip-to-chip gain variations.

The DAC full-scale gain-calibration system works by comparing an internal resistor to an external precision resistor of known

value. The two resistors are set up as a voltage divider that is connected between power and ground. The value of the

internal resistor changes with semiconductor process variations so by measuring the divider’s voltage output, using an ADC,

the process variation from nominal can be measured and this is used to correct the DAC gain. As all the DAC channels are

on the same monolithic chip, the channel-to-channel gain variation is very small and does not need to be trimmed.

There are two ADCs and either of the ADC inputs can be used to drive the auto-calibration circuit. The circuit uses the ADC

value, as decimated by the internal programmable decimation filters, to scale the master_trim value. Master_trim can be

programmed as normal but will be scaled by the ADC value when in automatic-calibration mode. In this mode, master_trim

can be set once by enabling automatic calibration, and the DAC output levels will be consistent across all DAC devices.

•

Full-scale gain-calibration is enabled using calib_en in Register 63: Auto Calibration.

•

calib_sel in Register 63: Auto Calibration selects which ADC to use

•

calib_latch in Register 63: Auto Calibration determines whether to use the new ADC correction value or ignore it.

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ADC values update at the ADC_CLK rate which is also programmable in Register 46: ADC Configuration.

The ADC decimation filters may also be programmed to a lower bandwidth to help smooth out any voltage transients on the

divider output.

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