ES9028PRO datasheet(23/57 Pages) ESS

23 / 57 page

July 6, 2020

CONFIDENTIAL INFORMATION v3.6

ES9028PRO 32-Bit HyperStream® II 8-Channel Audio DAC

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-

8800 • Fax (408) 643-8801

Bits

[7]

[6:5]

[4]

[3:0]

Mnemonic

master_mode

master_div

128fs_mode

lock_speed

Default

1’b0

2’b00

1’b0

4’d0

Bit

Mnemonic

Description

[7]

master_mode

Enables master mode which causes the SABRE DAC to derive the

DATA_CLK and DATA1 signals when in I2S mode. Can also be enabled

when in DSD mode to enable DATA_CLK only.

•

1’b1: enables master mode

•

1’b0: disables master mode (default)

[6:5]

master_div

Sets the frame clock (DATA1) and DATA_CLK frequencies when in

master mode. This register is used when in normal synchronous

operation.

•

2’b00: DATA_CLK frequency = MCLK/2 (default)

•

2’b01: DATA_CLK frequency = MCLK/4

•

2’b10: DATA_CLK frequency = MCLK/8

•

2’b11: DATA_CLK frequency = MCLK/16

[4]

128fs_mode

Enables operation of the DAC while in synchronous mode with a

128*FSR MCLK in PCM normal or OSF bypass mode only.

•

1’b1: enables MCLK = 128*FSR mode

•

1’b0: disables MCLK = 128*FSR mode (default)

[3:0]

lock_speed

Sets the number of audio samples required before the DPLL and jitter

eliminator lock to the incoming signal. More audio samples give a better

initial estimate of the MCLK/FSR ratio at the expense of a longer locking

interval.

•

4’d0: 16384 FSL edges (default)

•

4’d1: 8192 FSL edges

•

4’d2: 5461 FSL edges

•

4’d3: 4096 FSL edges

•

4’d4: 3276 FSL edges

•

4’d5: 2730 FSL edges

•

4’d6: 2340 FSL edges

•

4’d7: 2048 FSL edges

•

4’d8: 1820 FSL edges

•

4’d9: 1638 FSL edges

•

4’d10: 1489 FSL edges

•

4’d11: 1365 FSL edges

•

4’d12: 1260 FSL edges

•

4’d13: 1170 FSL edges

•

4’d14: 1092 FSL edges

•

4’d15: 1024 FSL edges

Note: FSL=FSR except in DSD Mode FSL=FSR*64

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