EM78P152S datasheet(16/52 Pages) ETC1

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EM78P152/3S

8-Bit Microcontroller with OTP ROM

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Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

5.2.8 IOCF (Interrupt Mask Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EXIE

ICIE

TCIE

Bits 7~3:

Not used

Individual interrupt is enabled by setting its associated control bit in the

IOCF to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the

DISI instruction. Refer to Figure 9.

Bit 2 (EXIE): EXIF interrupt enable bit

0 : disable EXIF interrupt

1 : enable EXIF interrupt

Bit 1 (ICIE):

ICIF interrupt enable bit

0 : disable ICIF interrupt

1 : enable ICIF interrupt

Bit 0 (TCIE): TCIF interrupt enable bit

0 : disable TCIF interrupt

1 : enable TCIF interrupt

The IOCF register is both readable and writable.

5.3 TCC/WDT and Prescaler

There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is

available for the TCC only or the WDT only at the same time and the PAB bit of the

CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits

determine the ratio. The prescaler is cleared each time the instruction is written to TCC

under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared

by the “WDTC” or “SLEP” instructions. Figure 5-4 depicts the circuit diagram of

TCC/WDT.

R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal or

external clock input (edge selectable from TCC pin). If the TCC signal source is

from an internal clock, TCC will be incremented by 1 at every instruction cycle

(without prescaler). Referring to Figure 5-4, CLK=Fosc/2 or CLK=Fosc/4,

depends on the Code Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and

CLK=Fosc/4 is used if CLK bit is "1". If the TCC signal source is from an external

clock input, TCC is incremented by 1 at every falling edge or rising edge of the

TCC pin.

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep

running even when the oscillator driver has been turned off (i.e. in sleep mode).

During normal operation or sleep mode, a WDT time-out (if enabled) will cause the

device to reset. The WDT can be enabled or disabled any time during normal

mode by software programming. Refer to WDTE bit of the IOCE register. Without

prescaler, the WDT time-out period is approximately 18 ms1 (default).

Note: Vdd = 5V, set up time period = 16.5ms ± 30%

Vdd = 3V, set up time period = 18ms ± 30%

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