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WM8774IFT 数据表(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8774IFT 数据表(HTML) 11 Page - Wolfson Microelectronics plc |
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11 / 42 page  Product Preview WM8774 PP Rev 1.0 June 2002 11 MPU INTERFACE TIMING t RCHO t RCSU CE CL DI t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS RESETB Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT CE to RESETB hold time tRCSU 20 ns RESETB to CL setup time tRCHO 20 ns CL rising edge to CE rising edge tSCS 60 ns CL pulse cycle time tSCY 80 ns CL pulse width low tSCL 30 ns CL pulse width high tSCH 30 ns DI to CL set-up time tDSU 20 ns CL to DI hold time tDHO 20 ns CE pulse width low tCSL 20 ns CE pulse width high tCSH 20 ns CE rising to CL rising tCSS 20 ns Table 4 3 Wire SPI compatible Control Interface Input Timing Information |
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