WM8774IFT datasheet(32/42 Pages) WOLFSON

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WM8774

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PP Rev 1.0 June 2002

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

BCP

BITCLK Polarity

0: Normal - DIN, DACLRC & ADCLRC sampled on rising

edge of BCLK; DOUT changes on falling edge of BCLK.

1: Inverted - DIN, DACLRC & ADCLRC sampled on falling

edge of BCLK; DOUT changes on rising edge of BCLK.

5:4

WL[1:0]

Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justified mode)

ADCHPD

ADC Highpass Filter Disable:

0: Highpass Filter enabled

1: Highpass Filter disabled

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC ratio select:

010: 256fs

011: 384fs

100: 512fs

ADCOSR

ADC oversample rate select

0: 128x oversampling

1: 64x oversampling

6:4

DACRATE[2:0]

010

Master Mode MCLK:DACLRC ratio select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

10111

Master Mode

control

Maser/Slave interface mode select

0: Slave Mode – ADCLRC, DACLRC and BCLK are inputs

1: Master Mode – ADCLRC, DACLRC and BCLK are outputs

PWDN

Chip Powerdown Control (works in tandem with ADCD and

DACD):

0: All circuits running, outputs are active

1: All circuits in power save mode, outputs muted

ADCD

ADC powerdown:

0: ADC enabled

1: ADC disabled

11000

Powerdown

Control

DACD

DAC powerdown

0: DAC enabled

1: DAC disabled

4:0

LAG[4:0]

01100

(0dB)

Attenuation data for left channel ADC gain in 1dB steps

MUTE

Mute for Left channel ADC:

0: Mute off

1: Mute on

LRBOTH

Setting LRBOTH will write the same gain value to LAG[4:0] and

RAG[4:0]

11001

Attenuation

ADCL

ADCMUTE

Mute for Left and Right channel ADC:

0: Mute off

1: Mute on

WM8774IFT 数据表(PDF) 32 Page - Wolfson Microelectronics plc

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