数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

WM8774IFT 数据表(PDF) 19 Page - Wolfson Microelectronics plc

部件名 WM8774IFT
功能描述  24 - bit, 192kHz 8 - Channel Input Stereo Codec
PDF  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8774IFT 数据表(HTML) 19 Page - Wolfson Microelectronics plc

Back Button WM8774IFT Datasheet HTML 15Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 16Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 17Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 18Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 19Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 20Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 21Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 22Page - Wolfson Microelectronics plc WM8774IFT Datasheet HTML 23Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 42 page
background image
Product Preview
WM8774
PP Rev 1.0 June 2002
19
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
CE
CL
DI
Figure 16 3-Wire SPI Compatible Interface
1.
B[15:9] are Control Address Bits
2.
B[8:0] are Control Data Bits
3.
CE is edge sensitive – the data is latched on the rising edge of CE.
CONTROL INTERFACE REGISTERS
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10110
Interface Control
1:0
FMT[1:0]
10
Interface format Select
00 : right justified mode
01: left justified mode
10: I
2S mode
11: DSP (early or late) mode
In left justified, right justified or I
2S modes, the LRP register bit controls the polarity of
ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the
opposite of that shown,
Figure 10 and. Note that if this feature is used as a means of swapping the left and right channels, a
1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select
between early and late modes.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
In left/right/ I
2S modes:
ADCLRC/DACLRC Polarity (normal)
0 : normal ADCLRC/DACLRC
polarity
1: inverted ADCLRC/DACLRC
polarity
10110
Interface Control
2
LRP
0
In DSP mode:
0 : Early DSP mode
1: Late DSP mode
By default, ADCLRC/DACLRC and DIN is sampled on the rising edge of BCLK and should ideally
change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN on the rising edge
of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of
BCLK to the inverse of that shown in,
Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10110
Interface Control
3
BCP
0
BCLK Polarity (DSP modes)
0 : normal BCLK polarity
1: inverted BCLK polarity



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com