WM8774IFT datasheet(17/42 Pages) WOLFSON

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WM8774

PP Rev 1.0 June 2002

2S MODE

In I

2S mode, the MSB of DIN is sampled by the WM8774 on the second rising edge of BCLK

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of

BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 11 I

2S Mode TIming Diagram

DSP EARLY MODE

In DSP early mode, the MSB of DAC channel left data is sampled by the WM8774 on the second

rising edge on BCLK following a DACLRC rising edge (Figure 12).

DACLRC

BCK

DIN

Word Length (IWL)

1/fs

CHANNEL LEFT

n-1

LSB

MSB

n-1

CHANNEL RIGHT

NO VALID DATA

1 BCLK

Figure 12 DSP Early Mode Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of

BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK.

The right channel ADC data is contiguous with the left channel data (Figure 13)

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCLK

Figure 13 DSP Early Mode Timing Diagram – ADC Data Output

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