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WM8774IFT 数据表(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8774IFT 数据表(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 42 page  WM8774 Product Preview PP Rev 1.0 June 2002 30 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6:0 LA[6:0] 1111111 (0dB) Attenuation data for Left channel DACL in 1dB steps. See Table 10 7 LZCEN 0 DACL zero cross detect enable 0: zero cross disabled 1: zero cross enabled 00000 Analogue Attenuation DACL 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACL in intermediate latch (no change to output) 1: Store DACL and update attenuation on all channels. 6:0 RA[6:0] 1111111 (0dB) Attenuation data for Right channel DACR in 1dB steps. See Table 10 7 RZCEN 0 DACR zero cross detect enable 0: zero cross disabled 1: zero cross enabled 00001 Analogue Attenuation DACR 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACR in intermediate latch (no change to output) 1: Store DACR and update attenuation on all channels. 6:0 MASTA[6:0] 1111111 (0dB) Attenuation data for all DAC gains in 1dB steps. See Table 10 7 MZCEN 0 Master zero cross detect enable 0: zero cross disabled 1: zero cross enabled 01000 Analogue Master Attenuation (both channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store gains in intermediate latch (no change to output) 1: Store gains and update attenuation on all channels. 7:0 LDA[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 11 01001 Digital Attenuation DACL 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on all channels 7:0 RDA[6:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 11 01010 Digital Attenuation DACR 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on all channels. 7:0 MASTDA[7:0] 11111111 (0dB) Digital Attenuation data for both DAC channels in 0.5dB steps. See Table 11 10001 Master Digital Attenuation (both channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. 10010 Phase swaps 1:0 PH 00 Controls phase of DAC outputs 0: Sets non inverted output phase 1: inverts phase of DAC output |
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