WM8774IFT datasheet(18/42 Pages) WOLFSON

18 / 42 page

WM8774

Product Preview

PP Rev 1.0 June 2002

DSP LATE MODE

In DSP late mode, the MSB of DAC channel left data is sampled by the WM8774 on the first BCLK

rising edge following a DACLRC rising edge (Figure 14).

DACLRC

BCK

DIN

Word Length (WL)

1/fs

CHANNEL LEFT

n-1

LSB

MSB

n-1

CHANNEL RIGHT

NO VALID DATA

Figure 14 DSP Late Mode Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of

BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The

right channel ADC data is contiguous with the left channel data (Figure 15).

ADCLRC

BCK

DOUT

Word Length (WL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 15 DSP Late Mode Timing Diagram – ADC Data Output

In both early and late DSP modes, DACL is always sent first, followed immediately by DACR. No

BCLK edges are allowed between the data words.

CONTROL INTERFACE OPERATION

The WM8774 is controlled using a 3-wire serial interface a SPI compatible.

The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI

may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD.

RESETB is also 5V tolerant.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

DI is used for the program data, CL is used to clock in the program data and CE is used to latch the

program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in

Figure 16.

WM8774IFT 数据表(PDF) 18 Page - Wolfson Microelectronics plc

WM8774IFT 数据表(HTML) 18 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载