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WM8774

PP Rev 1.0 June 2002

27

ADC INPUT GAIN

Registers LAG and RAG control the left and right channel gain into the stereo ADC in 1dB steps from

+19dB to –12dB Table 8 shows how the attenuation levels are selected from the 5-bit words.

L/RAG[6:0]

ATTENUATION LEVEL

0

-12dB

:

:

01100

0dB

:

:

11111

+19dB

Table 12 ADC Gain Control

ADC HIGHPASS FILTER DISABLE

The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled

using software control bit ADCHPD.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10110

ADC control

8

ADCHPD

0

ADC Highpass filter disable:

0: Highpass filter enabled

1: Highpass filter disabled

ADC INPUT MUX AND POWERDOWN CONTROL

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

LMX[2:0]

000

ADC left channel input mux control

bits (see Table 13)

6:4

RMX[2:0]

000

ADC right channel input mux

control bits (see Table 13)

11011

ADC mux and

powerdown

control

8

AINPD

1

Input mux and buffer powerdown

0: Input mux and buffer

enabled

1: Input mux and buffer

powered down

Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default

is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel

mux inputs are switched to buffered VMIDADC.

LMX[2:0]

LEFT ADC INPUT

RMX[2:0]

RIGHT ADC INPUT

000

AIN1L

000

AIN1R

001

AIN2L

001

AIN2R

010

AIN3L

010

AIN3R

011

AIN4L

011

AIN4R

100

AIN5L

100

AIN5R

101

AIN6L

101

AIN6R

110

AIN7L

110

AIN7R

111

AIN8L

111

AIN8R

Table 13 ADC Input Mux Control