AT25QL321 datasheet(12/79 Pages) DIALOG

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AT25QL321

DS-25QL321–131C–5/2017

Note: 1. When SRP1, SRP0=(1,0), a power down, power-up cycle will change SRP1, SRP0 to(0,0) state.

6.4

Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad operation.

When the QE pin is set to a 1 (factory default) the Quad IO2 and IO3 pins are enabled. When the QE bit is set to a 0

state the WP pin and HOLD are enabled. WARNING : The QE bit should never be set to a 1 during standard SPI or

Dual SPI operation if the WP or HOLD pins are tied directly to the power supply or ground.

6.5

Erase/Program Suspend Status (SUS)

The Suspend Status bit (SUS) is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program

Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power

down, power‐up cycle.

SRP1

SRP0

Status

Description

Software

WP pin no control. The register can be written to

Hardware

When WP pin is low the Status Register locked and can not

Hardware

Unprotected

When WP pin is high the Status register is unlocked and can be written to

after a Write Enable instruction, WEL=1

Power Supply

Status Register is protected and cannot be written to again until the next

power down, power‐up cycle(1)

One Time

Status Register is permanently protected and cannot be written to.

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