AT25QL321 datasheet(21/79 Pages) DIALOG

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AT25QL321

DS-25QL321–131C–5/2017

Figure 7-9. Write Status Register-2 Instruction (QPI Mode)

7.8

Read Data (03h)

The Read Data instruction is to read data out from the device. The instruction is initiated by driving the CS pin low and then

sending the instruction code “03h” with following a 24‐bit address (A23- A0) into the SI pin. After the address is received, the

data byte of the addressed memory location will be shifted out on the SO pin at the falling edge of SCK with most significant bit

(MSB) first. The address is automatically incremented to the next higher address after byte of data is shifted out allowing for a

continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock

continues. The instruction is completed by driving CS high. The Read Data instruction sequence is shown in Figure 7-10. If a

Read Data instruction is issued while an Erase, Program or Write Status Register cycle is in process (BUSY=1) the instruction

is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C to a

maximum of fR (see AC Electrical Characteristics).

Figure 7-10. Read Data Instruction

7.9

Fast Read (0Bh)

The Fast Read instruction is high speed reading mode that it can operate at the highest possible frequency of FR. The address

is latched on the rising edge of the SCK. After the 24‐bit address, this is accomplished by adding “dummy” clocks as shown in

Figure 7-11. The dummy clocks means the internal circuits require time to set up the initial address. During the dummy clocks,

the data value on the SO pin is a “don’t care”. Data of each bit shifts out on the falling edge of SCK.

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