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AT25QL321

DS-25QL321–131C–5/2017

7.17 Block Erase (20h)

The Block Erase instruction is to erase the data of the selected sector as being “1”. The instruction is used for 4K-byte

Block. Prior to the Block Erase Instruction, the Write Enable instruction must be issued. The instruction is initiated by

driving the CS pin low and shifting the instruction code “20h” followed a 24-bit Block address (A23-A0). (Please refer to

Figure 7-26 and Figure 7-27). The CS pin must go high after the eighth bit of the last byte has been latched in,

otherwise, the Block Erase instruction will not be executed. After CS goes high, the self-timed Block Erase instruction will

commence for a time duration of tSE (See AC Characteristics).

While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL)

bit in the Status Register is cleared to 0.

Figure 7-26. Block Erase Instruction (SPI Mode)

Figure 7-27. Block Erase Instruction (QPI Mode)

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