AT25QL321 datasheet(33/79 Pages) DIALOG

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AT25QL321

DS-25QL321–131C–5/2017

7.18 32KB Block Erase (52h)

The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction is used for 32K-byte

Block erase operation. Prior to the Block Erase Instruction, a Write Enable instruction must be issued. The instruction is

initiated by driving the CS pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0).

(Please refer to Figure 7-28 and Figure 7-29). The CS pin must go high after the eighth bit of the last byte has been

latched in, otherwise, the Block Erase instruction will not be executed. After CS is driven high, the self-timed Block Erase

instruction will commence for a time duration of tBE1 (See AC Characteristics).

While the Block Erase cycle is in progress, the Read Status Register instruction may still be read the status of the

BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the

device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in

the Status Register is cleared to 0.

Figure 7-28. 32KB Block Erase Instruction (SPI Mode)

Figure 7-29. 32KB Block Erase Instruction (QPI Mode)

AT25QL321 数据表(PDF) 33 Page - Dialog Semiconductor