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AT25QL321

DS-25QL321–131C–5/2017

Figure 7-1. Write Enable Instruction for SPI Mode (left) and QPI Mode (right)

7.3

Write Enable for Volatile Status Register (50h)

This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting

for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the

volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued

prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7-2) will

not set the Write Enable Latch (WEL) bit. Once Write Enable for Volatile Status Register is set, a Write Enable

instruction should not have been issued prior to setting Write Status Register instruction (01h or 31h). When Write

Enable for Volatile Status Register (50h) is set in QPI Mode, the SUS bit (S15) and Reserved bits (S13, S12, S11 and

S10) of the Status Register-2 must be driven to high after Write Status Register instruction (01h). Once Read Status

Status Register-2 are ignored.

Figure 7-2. Write Enable for Volatile Status Register Instruction for SPI Mode (left) and QPI Mode (right)

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