AT25QL321 datasheet(29/79 Pages) DIALOG

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AT25QL321

DS-25QL321–131C–5/2017

7.15 Page Program (02h)

The Page Program instruction is for programming the memory to be “0”. A Write Enable instruction must be issued

before the device accept the Page Program Instruction (Status Register bit WEL=1). After the Write Enable (WREN)

instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction is entered by driving the

CS pin low and then sending the instruction code “02h” with following a 24-bits address (A23-A0) and at least one data

byte, into the SI pin. The CS pin must be driven low for the entire time of the instruction while data is being sent to the

device. (Please refer to Figure 7-22 and Figure 7-23).

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set

to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing

will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without

having any effect on other bytes within the same page. One condition to perform a partial page program is that the

number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing

will wrap to the beginning of the page and overwrite previously sent data

The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page

Program instruction will not be executed. After CS is driven high, the self-timed Page Program instruction will

commence for a time duration of tPP (See AC Characteristics). While the Page Program cycle is in progress, the Read

Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the

Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions

again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 7-22. Page Program Instruction (SPI Mode)

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