ADP5075

Data Sheet

Rev. B | Page 6 of 19

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

1

AVIN

PVIN

SW

VREG

SLEW

SS

GND SYNC/FREQ EN

VREF

FB

COMP

A

B

C

D

23

BALL A1

INDICATOR

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin

No.

Mnemonic

Description

A1

AVIN

System Power Supply for the ADP5075.

A2

PVIN

Power Input for the Inverting Regulator.

A3

SW

Switching Node for the Inverting Regulator.

B1

VREG

Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and GND.

B2

SLEW

Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the FET driving the SW pin. For the fastest slew

rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the slowest

slew rate (best noise performance), connect the SLEW pin to ground.

B3

SS

Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start

time, connect a resistor between the SS pin and GND.

C1

GND

Ground.

C2

SYNC/FREQ

Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high. To

set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency,

connect the SYNC/FREQ pin to an external clock.

C3

EN

Inverting Regulator Precision Enable. The EN pin is compared to an internal precision reference to enable the

inverting regulator output.

D1

VREF

Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and ground.

D2

FB

Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting

regulator output capacitor and VREF to program the output voltage.

D3

COMP

Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and GND.