ADP5075

Data Sheet

Rev. B | Page 18 of 19

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators but is particularly

important for regulators with high switching frequencies. To

achieve high efficiency, good regulation, good stability, and low

noise, a well designed PCB layout is required. Follow these

guidelines when designing PCBs:



Keep the input bypass capacitor, CIN, close to the PVIN pin

and the AVIN pin. Route each of these pins individually to

the pad of this capacitor to minimize noise coupling

between the power inputs, rather than connecting the three

pins at the device. A separate capacitor can be used on the

AVIN pin for the best noise performance.



Keep the high current paths as short as possible. These

paths include the connections between CIN, L1, D1,

COUT, and GND and their connections to the ADP5075.



Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and EMI.



Avoid routing high impedance traces near any node con-

nected to the SW pin or near inductor L1 to prevent

radiated switching noise injection.



Place the feedback resistors as close to the FB pin as possible

to prevent high frequency switching noise injection.



Route a trace to RFT directly from the COUT pad for

optimum output voltage sensing.



Place the compensation components as close as possible to

COMP. Do not share vias to the ground plane with the

feedback resistors to avoid coupling high frequency noise into

the sensitive COMP pin.



Place the CVREF and CVREG capacitors as close to the

VREG and VREF pins as possible. Ensure that short traces

are used between VREF and RFB.

L1

D1

RC

RFT

RFB

CVREG

COUT1

CIN

CVREF

CC

Figure 28. Suggested Layout for 5 mm × 6 mm, +3.3 V Input to −5 V Output Application

(Dashed Line Is Connected on the Internal Layer of the PCB; Other Vias Connected to the Ground Plane;

SS, EN, SLEW, and SYNC/FREQ Connections Not Shown for Clarity and Are Typically Connected on an Internal Layer)