Data Sheet

ADP5075

Rev. B | Page 11 of 19

THEORY OF OPERATION

VIN

HV

BAND GAP

SW

FB

INVERTER

PWM CONTROL

PVIN

ERROR AMP

HV

REGULATOR

EN

AVIN

VREG

COMP

SLEW

SYNC/FREQ

SS

GND

CURRENT

SENSE

START-UP

TIMERS

PLL

4µA

REF

CONTROL

OSCILLATOR

SLEW

INVERTER_ENABLE

EN

L1

D1

THERMAL

SHUTDOWN

UVLO

OVP

VREF

VREG

FB

REFERENCE

GENERATOR

REF_1.6V

REF_1.6V

REF

Figure 23. Functional Block Diagram

PWM MODE

The inverting regulator in the ADP5075 operates at a fixed fre-

quency set by an internal oscillator. At the start of each oscillator

cycle, the MOSFET switch turns on, applying a positive voltage

until the current sense signal crosses the peak inductor current

threshold that turns off the MOSFET switch; this threshold is set

by the error amplifier output. During the MOSFET off time, the

inductor current declines through the external diode until the next

oscillator clock pulse starts a new cycle. The ADP5075 regulates the

output voltage by adjusting the peak inductor current threshold.

PSM MODE

During light load operation, the regulators can skip pulses to

maintain output voltage regulation. Skipping pulses increases

the device efficiency.

UNDERVOLTAGE LOCKOUT (UVLO)

The undervoltage lockout circuitry monitors the AVIN pin voltage

the regulator turns off. After the AVIN pin voltage rises above

regulator is enabled.

OSCILLATOR AND SYNCHRONIZATION

A phase-locked loop (PLL)-based oscillator generates the internal

clock and offers a choice of two internally generated frequency

options or external clock synchronization. The switching frequency

is configured using the SYNC/FREQ pin options shown in Table 6.

For external synchronization, connect the SYNC/FREQ pin to a

suitable clock source. The PLL locks to an input clock within

Table 6. SYNC/FREQ Pin Options

SYNC/FREQ Pin

Switching Frequency

High

2.4 MHz

Low

1.2 MHz

External Clock

1× clock frequency

INTERNAL REGULATORS

The internal VREG regulator in the ADP5075 provides a stable

power supply for the internal circuitry. The VREG supply provides

a high signal for device configuration pins but must not be used

to supply external circuitry.

The VREF regulator provides a reference voltage for the inverting

regulator feedback network to ensure a positive feedback voltage

on the FB pin.

A current-limit circuit is included for both internal regulators to

protect the circuit from accidental loading.

PRECISION ENABLING

The ADP5075 has an enable pin that features a precision enable

circuit with an accurate reference voltage. This reference allows the

ADP5075 to be sequenced easily from other supplies. It can also

be used as a programmable UVLO input by using a resistor divider.

The enable pin has an internal pull-down resistor that defaults

to off when the pin is floating.

reference level, the regulator is enabled.