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STM32F107VC 数据表(PDF) 74 Page - STMicroelectronics |
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STM32F107VC 数据表(HTML) 74 Page - STMicroelectronics |
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74 / 108 page  Electrical characteristics STM32F105xx, STM32F107xx 74/108 DocID15274 Rev 10 CAN (controller area network) interface Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 51. Dynamic characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 10 - - ns tih(RXD) Receive data hold time 10 - - ns tsu(DV) Data valid setup time 10 - - ns tih(DV) Data valid hold time 10 - - ns tsu(ER) Error setup time 10 - - ns tih(ER) Error hold time 10 - - ns td(TXEN) Transmit enable valid delay time 14 16 18 ns td(TXD) Transmit data valid delay time 13 16 20 ns Table 52. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.6 V VREF+ Positive reference voltage - 2.4 - VDDA V IVREF Current on the VREF input pin - - 160(1) 220(1) µA fADC ADC clock frequency - 0.6 - 14 MHz fS(2) Sampling rate - 0.05 - 1 MHz fTRIG(2) External trigger frequency fADC = 14 MHz - - 823 kHz - - - 17 1/fADC VAIN Conversion voltage range(3) - 0 (VSSA or VREF- tied to ground) - VREF+ V RAIN(2) External input impedance See Equation 1 and Table 53 for details - - 50 k Ω RADC(2) Sampling switch resistance - - - 1 k Ω CADC(2) Internal sample and hold capacitor - - - 8 pF tCAL(2) Calibration time fADC = 14 MHz 5.9 µs - 83 1/fADC |
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