STM32F107VC datasheet(21/108 Pages) STMICROELECTRONICS

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STM32F105xx, STM32F107xx

Description

107

•

32-bit CRC generation and removal

•

Several address filtering modes for physical and multicast address (multicast and

group addresses)

•

32-bit status code for each transmitted or received frame

•

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the

receive FIFO are both 2 Kbytes, that is 4 Kbytes in total

•

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with

the timestamp comparator connected to the TIM2 trigger input

•

Triggers interrupt when system time becomes greater than target time

2.3.21

Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to

1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)

are not shared with any other peripheral.

2.3.22

Universal serial bus on-the-go full-speed (USB OTG FS)

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full-

speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG

FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0

specification. It has software-configurable endpoint setting and supports suspend/resume.

The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by

a PLL connected to the HSE oscillator. The major features are:

•

1.25 KB of SRAM used exclusively by the endpoints (not shared with any other

peripheral)

•

4 bidirectional endpoints

•

HNP/SNP/IP inside (no need for any external resistor)

•

for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

•

the SOF output can be used to synchronize the external audio DAC clock in

isochronous mode

•

in accordance with the USB 2.0 Specification, the supported transfer speeds are:

–

in Host mode: full speed and low speed

–

in Device mode: full speed

2.3.23

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

STM32F107VC 数据表(PDF) 21 Page - STMicroelectronics

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