AD9959SLASHPCBZ datasheet(25/44 Pages) AD

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Data Sheet

AD9959

Rev. C | Page 25 of 44

LINEAR SWEEP MODE

Linear sweep mode enables the user to sweep frequency, phase,

or amplitude from a starting point (S0) to an endpoint (E0).

The purpose of linear sweep mode is to provide better band-

width containment compared to direct modulation by replacing

greater instantaneous changes with more gradual, user-defined

changes between S0 and E0.

In linear sweep mode, S0 is loaded into the Channel Word 0

and E0 is always loaded into Channel Word 1 (Register 0x0A).

If E0 is configured for frequency sweep, the resolution is 32 bits,

phase sweep is 14 bits, and amplitude sweep is 10 bits. When

sweeping phase or amplitude, the word value must be MSB aligned

in the Channel Word 1 register. The unused bits are don’t care

bits. The profile pins are used to trigger and control the direction

of the linear sweep for frequency, phase, and amplitude. All

channels can be programmed separately for a linear sweep. In

linear sweep mode, Profile Pin P0 is dedicated to Channel 0.

Profile Pin P1 is dedicated to Channel 1, and so on.

The AD9959 has the ability to ramp up or ramp down (RU/RD)

the output amplitude (using the 10-bit output scalar) before and

after a linear sweep. If the RU/RD feature is desired, unused

profile pins or unused SDIO_1/SDIO_2/SDIO_3 pins can be

configured for the RU/RD operation.

To enable linear sweep mode for a particular channel, the AFP

select bits (CFR[23:22]), the modulation level bits (FR1[9:8]),

and the linear sweep enable bit (CFR[14]) are programmed.

The AFP select bits determine the type of linear sweep to be

performed. The modulation level bits must be set to 00 (two-

level) for that specific channel (see Table 19 and Table 20)

Table 19. Linear Sweep Parameter to Sweep

AFP Select

(CFR[23:22])

Linear Sweep Enable

(CFR[14])

Description

N/A

Amplitude sweep

Frequency sweep

Phase sweep

Table 20. Modulation Level Assignments

Modulation Level (FR1[9:8])

Description

00 (Required in Linear Sweep)

Two-level modulation

Four-level modulation

Eight-level modulation

16-level modulation

Setting the Slope of the Linear Sweep

The slope of the linear sweep is set by the intermediate step size

(delta-tuning word) between S0 and E0 and the time spent

(sweep ramp rate word) at each step. The resolution of the

delta-tuning word is 32 bits for frequency, 14 bits for phase, and

10 bits for amplitude. The resolution for the delta ramp rate

word is eight bits.

In linear sweep, each channel is assigned a rising delta word

(RDW, Register 0x08) and a rising sweep ramp rate word

(RSRR, Register 0x07). These settings apply when sweeping up

toward E0. The falling delta word (FDW, Register 0x09) and

falling sweep ramp rate (FSRR, Register 0x07) apply when

sweeping down toward S0. Figure 36 displays a linear sweep up

and then down using a profile pin. Note that the linear sweep

no-dwell bit is disabled; otherwise, the sweep accumulator

returns to 0 upon reaching E0.

RDW

RSRR

FSRR

∆f,p,a

FDW

TIME

PROFILE PIN

∆f,p,a

∆t

Figure 36. Linear Sweep Parameters

For a piecemeal or a nonlinear transition between S0 and E0,

the delta-tuning words and ramp rate words can be repro-

grammed during the transition to produce the desired response.

The formulas for calculating the step size of RDW or FDW for

delta frequency, delta phase, or delta amplitude are as follows:

SYSCLK

RDW



















(Hz)



















360

RDW

ΔΦ

1024



















RDW

(DAC full-scale current)

The formula for calculating delta time from RSRR or FSRR is





CLK

SYNC

RSRR





At 500 MSPS operation (SYNC_CLK = 125 MHz), the maxi-

mum time interval between steps is 1/125 MHz × 256 = 2.048 μs.

The minimum time interval is (1/125 MHz) × 1 = 8.0 ns.

The sweep ramp rate block (timer) consists of a loadable 8-bit

down counter that continuously counts down from the loaded

value to 1. When the ramp rate timer equals 1, the proper ramp rate

value is loaded and the counter begins counting down to 1 again.

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