AD9959SLASHPCBZ datasheet(42/44 Pages) AD

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AD9959

Data Sheet

Rev. C | Page 42 of 44

Channel Frequency Tuning Word 0 (CFTW0)—Address 0x04

Four bytes are assigned to this register.

Table 35. Description for CFTW0

Bit

Mnemonic

Description

31:0

Frequency Tuning Word 0

Frequency Tuning Word 0 for each channel.

Channel Phase Offset Word 0 (CPOW0)—Address 0x05

Two bytes are assigned to this register.

Table 36. Description for CPOW0

Bit

Mnemonic

Description

15:14

Open

13:0

Phase Offset Word 0

Phase Offset Word 0 for each channel

Amplitude Control Register (ACR)—Address0x06

Three bytes are assigned to this register.

Table 37. Description for ACR

Bit

Mnemonic

Description

23:16

Amplitude ramp rate

Amplitude ramp rate value.

15:14

Increment/decrement

step size

Amplitude increment/decrement step size.

Open

Amplitude multiplier

enable

0 = amplitude multiplier is disabled. The clocks to this scaling function (auto RU/RD) are stopped

for power saving, and the data from the DDS core is routed around the multipliers (default).

1 = amplitude multiplier is enabled.

Ramp-up/ramp-down

This bit is valid only when ACR[12] is active high.

enable

0 = when ACR[12] is active, Logic 0 on ACR[11] enables the manual RU/RD operation. See the

Output Amplitude Control Mode section for details (default).

1 = if ACR[12] is active, a Logic 1 on ACR[11] enables the auto RU/RD operation. See the Output

Amplitude Control Mode section for details.

Load ARR at

I/O_UPDATE

0 = the amplitude ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded due

to an I/O_UPDATE input signal (default).

1 = the amplitude ramp rate timer is loaded upon timeout (timer = 1) or at the time of an

I/O_UPDATE input signal.

9:0

Amplitude scale factor

Amplitude scale factor for each channel.

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