AD9959

Data Sheet

Rev. C | Page 30 of 44

I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK

RELATIONSHIPS

I/O_UPDATE and SYNC_CLK are used together to transfer

data from the serial I/O buffer to the active registers in the

device. Data in the buffer is inactive.

SYNC_CLK is a rising edge active signal. It is derived from

the system clock and a divide-by-4 frequency divider. The

SYNC_CLK, which is externally provided, can be used to

synchronize external hardware to the AD9959 internal clocks.

I/O_UPDATE initiates the start of a buffer transfer. It can be

sent synchronously or asynchronously relative to the SYNC_CLK.

If the setup time between these signals is met, then constant

latency (pipeline) to the DAC output exists. For example, if

repetitive changes to phase offset via the SPI port is desired, the

latency of those changes to the DAC output is constant; otherwise,

a time uncertainty of one SYNC_CLK period is present.

The I/O_UPDATE is essentially oversampled by the SYNC_CLK.

Therefore, I/O_UPDATE must have a minimum pulse width

greater than one SYNC_CLK period.

The timing diagram shown in Figure 40 depicts when data in

the buffer is transferred to the active registers.

SYNC_CLK

SYSCLK

AB

NN + 1

N – 1

DATA IN

REGISTERS

DATA IN

I/O BUFFERS

N

N + 1

N + 2

I/O_UPDATE

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

Figure 40. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers