Data Sheet

AD9959

Rev. C | Page 39 of 44

DESCRIPTIONS FOR CONTROL REGISTERS

Channel Select Register (CSR)—Address 0x00

One byte is assigned to this register.

The CSR determines if channels are enabled or disabled by the status of the four channel enable bits. All four channels are enabled by

their default state. The CSR also determines which serial mode of operation is selected. In addition, the CSR offers a choice of MSB first

or LSB first format.

Table 31. Bit Descriptions for CSR

Bit

Mnemonic

Description

7:4

Channel [3:0] enable

Bits are active immediately after being written. They do not require an I/O update to take effect.

There are four sets of channel registers and profile (channel word) registers, one per channel. This

is not shown in the channel register map or the profile register map. The addresses of all channel

registers and profile registers are the same for each channel. Therefore, the channel enable bits

distinguish the channel registers and profile registers values of each channel. For example,

1001 = only Channel 3 and Channel 0 receive commands from the channel registers and profile

registers.

0010 = only Channel 1 receives commands from the channel registers and profile registers.

3

Must be 0

Must be set to 0.

2:1

Serial I/O mode select

00 = single-bit serial (2-wire mode).

01 = single-bit serial (3-wire mode).

10 = 2-bit serial mode.

11 = 4-bit serial mode.

See the Serial I/O Modes of Operation section for more details.

0

LSB first

0 = the serial interface accepts serial data in MSB first format (default).

1 = the serial interface accepts serial data in LSB first format.

Function Register 1 (FR1)—Address 0x01

Three bytes are assigned to this register. FR1 is used to control the mode of operation of the chip.

Table 32. Bit Descriptions for FR1

Bit

Mnemonic

Description

23

VCO gain control

0 = the low range (system clock below 160 MHz) (default).

1 = the high range (system clock above 255 MHz).

22:18

PLL divider ratio

If the value is 4 or 20 (decimal) or between 4 and 20, the PLL is enabled and the value sets the

multiplication factor. If the value is outside of 4 and 20 (decimal), the PLL is disabled.

17:16

Charge pump control

00 (default) = the charge pump current is 75 µA.

01 = charge pump current is 100 µA.

10 = charge pump current is 125 µA.

11 = charge pump current is 150 µA.

15

Open

14:12

Profile pin configuration (PPC)

The profile pin configuration bits control the configuration of the data and SDIO_x pins for the

different modulation modes. See the Modulation Mode section in this document for details.

11:10

Ramp-up/ramp-down (RU/RD)

The RU/RD bits control the amplitude ramp-up/ramp-down time of a channel. See the Output

Amplitude Control Mode section for more details.

9:8

Modulation level

The modulation (FSK, PSK, and ASK) level bits control the level (2/4/8/16) of modulation to be

performed for a channel. See the Modulation Mode section for more details.

7

Reference clock input

0 = the clock input circuitry is enabled for operation (default).

power-down

1 = the clock input circuitry is disabled and is in a low power dissipation state.

6

External power-down mode

0 = the external power-down mode is in fast recovery power-down mode (default). In this mode,

when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are

powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered

down.

1 = the external power-down mode is in full power-down mode. In this mode, when the

PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL,

which take a significant amount of time to power up.