Data Sheet

AD9959

Rev. C | Page 15 of 44

AD9959

(SLAVE 1)

AD9959

(MASTER)

CLOCK

SOURCE

AD9959

(SLAVE 2)

AD9959

(SLAVE 3)

REF_CLK

FPGA

DATA

SYNC_CLK

FPGA

DATA

SYNC_CLK

FPGA

DATA

SYNC_CLK

FPGA

DATA

SYNC_CLK

C1

S1

C2

S2

C3

S3

C4

S4

A1

A2

A4

A3

A_END

CENTRAL

CONTROL

AD9510

CLOCK DISTRIBUTOR

WITH

DELAY EQUALIZATION

SYNC_IN

SYNC_OUT

AD9510

SYNCHRONIZATION

DELAY EQUALIZATION

Figure 25. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC_CLK

ACOUSTIC OPTICAL

TUNABLE FILTER

OPTICAL FIBER CHANNEL

WITH MULTIPLE DISCRETE

WAVELENGTHS

OUTPUTS

INPUTS

SELECTABLE WAVELENGTH FROM EACH

CHANNEL VIA DDS TUNING AOTF

SPLITTER

WDM

SOURCE

WDM SIGNAL

CH0

CH1

CH2

CH3

CH0 CH1 CH2

CH3

CH0

CH1

AD9959

REFCLK

CH3

CH2

AMP

AMP

AMP

AMP

Figure 26. DDS Providing Stimulus for Acoustic Optical Tunable Filter

CH0

AD9959

REFCLK

CH1

ADCMP563

–

+

Figure 27. Agile Clock Source with Duty Cycle Control Using the Phase Offset Value in DDS to Change the DC Voltage to the Comparator