AD9959SLASHPCBZ datasheet(26/44 Pages) AD

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AD9959

Data Sheet

Rev. C | Page 26 of 44

This load and countdown operation continues for as long as the

timer is enabled. However, the count can be reloaded before

reaching 1 by either of the following two methods:



Method 1 is to change the profile pin. When the profile pin

changes from Logic 0 to Logic 1, the rising sweep ramp rate

(RSRR) register value is loaded into the ramp rate timer,

which then proceeds to count down as normal. When the

profile pin changes from Logic 1 to Logic 0, the falling sweep

ramp rate (FSRR) register value is loaded into the ramp

rate timer, which then proceeds to count down as normal.



Method 2 is to set the CFR[14] bit and issue an I/O update.

If sweep is enabled and CFR[14] is set, the ramp rate timer

loads the value determined by the profile pin. If the profile

pin is high, the ramp rate timer loads the RSRR; if the profile

pin is low, the ramp rate timer loads FSRR.

Frequency Linear Sweep Example: AFP Bits = 10

In the following example, the modulation level bits (FR1[9:8]) = 00,

the linear sweep enable bit (CFR[14]) = 1, and the linear sweep

no-dwell bit (CFR[15]) = 0.

In linear sweep mode, when the profile pin transitions from low

to high, the RDW is applied to the input of the sweep accumulator

and the RSRR register is loaded into the sweep rate timer.

The RDW accumulates at the rate given by the rising sweep

ramp rate (RSRR) bits until the output is equal to the CW1

held constant in frequency.

When the profile pin transitions from high to low, the FDW is

applied to the input of the sweep accumulator and the FSRR bits

are loaded into the sweep rate timer.

The FDW accumulates at the rate given by the falling sweep ramp

rate (FSRR) until the output is equal to the CFTW0 register

(Register 0x04) value. The sweep is then complete, and the output

is held constant in frequency.

See Figure 37 for the linear sweep block diagram. Figure 39

depicts a frequency sweep with no-dwell mode disabled. In this

mode, the output follows the state of the profile pin. A phase or

amplitude sweep works in the same manner.

LINEAR SWEEP NO-DWELL MODE

If the linear sweep no-dwell bit is set (CFR[15]), the rising sweep is

started in an identical manner to the dwell linear sweep mode;

that is, upon detecting Logic 1 on the profile input pin, the rising

sweep action is initiated. The word continues to sweep up at the

rate set by the rising sweep ramp rate at the resolution set by the

rising delta word until it reaches the terminal value. Upon reaching

the terminal value, the output immediately reverts to the starting

point and remains until Logic 1 is detected on the profile pin.

Figure 38 shows an example of the no-dwell mode. The points

labeled A indicate where a rising edge is detected on the profile

pin, and the points labeled B indicate where the AD9959 has

determined that the output has reached E0 and reverts to S0.

The falling sweep ramp rate bits (LSRR[15:8]) and the falling

delta word bits (FDW[31:0]) are unused in this mode.

RATE TIME

LOAD CONTROL

LOGIC

LIMIT LOGIC TO

KEEP SWEEP BETWEEN

S0 AND E0

RAMP RATE TIMER:

8-BIT LOADABLE DOWN COUNTER

ACCUMULATOR RESET

LOGIC

MUX

PROFILE PIN

MUX

FDW

RDW

FSRR

RSRR

PROFILE PIN

Z–1

CW1

SWEEP ACCUMULATOR

SWEEP ADDER

CFTW0

Figure 37. Linear Sweep Block Diagram (Frequency Sweep)

AD9959/PCBZ 数据表(PDF) 26 Page - Analog Devices

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