CC2430-RTR1-F64Z datasheet(32/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 32 of 232

12 8051 CPU

This section describes the 8051 CPU core,

with interrupts, memory and instruction set.

12.1 8051 CPU Introduction

The

CC2430 includes an 8-bit CPU core which

is an enhanced version of the industry

standard 8051 core.

The enhanced 8051 core uses the standard

8051 instruction set. Instructions execute

faster than the standard 8051 due to the

following:

•

One clock per instruction cycle is used

opposed

clocks

per

instruction cycle in the standard 8051.

•

Wasted bus states are eliminated.

Since an instruction cycle is aligned with

memory fetch when possible, most of the

single byte instructions are performed in a

single clock cycle. In addition to the speed

improvement, the enhanced 8051 core also

includes architectural enhancements:

•

A second data pointer.

•

Extended 18-source interrupt unit

The 8051 core is object code compatible with

the industry standard 8051 microcontroller.

That is, object code compiled with an industry

standard 8051 compiler or assembler executes

the

8051

core

and

functionally

equivalent. However, because the 8051 core

uses a different instruction timing than many

other 8051 variants, existing code with timing

loops may require modification. Also because

the peripheral units such as timers and serial

ports differ from those on a other 8051 cores,

code which includes instructions using the

peripheral units SFRs will not work correctly.

12.2 Reset

The

CC2430 has three reset sources. The

following events generate a reset:

•

Forcing RESET_N input pin low

•

A power-on reset condition

•

Watchdog timer reset condition

The initial conditions after a reset are as

follows:

•

I/O pins are configured as inputs with

pull-up

•

CPU program counter is loaded with

0x0000 and program execution starts

at this address

•

All peripheral registers are initialized to

their reset values (refer to register

descriptions)

•

Watchdog timer is disabled

12.3 Memory

The 8051 CPU has four different memory

spaces:

CODE. A 16-bit read-only memory space for

program memory.

DATA. An 8-bit read/write data memory space,

which can be directly or indirectly accessed by

a single CPU instruction. The lower 128 bytes

of the DATA memory space can be addressed

either directly or indirectly, the upper 128 bytes

only indirectly.

XDATA. A 16-bit read/write data memory

space access to which usually requires 4-5

CPU instruction cycles. Access to XDATA

memory is also slower in hardware than DATA

access as the CODE and XDATA memory

spaces share a common bus on the CPU core

and instruction pre-fetch from CODE can thus

not be performed in parallel with XDATA

accesses.

SFR. A 7-bit read/write register memory space

which can be directly accessed by a single

CPU instruction. For SFR registers whose

address is divisible by eight, each bit is also

individually addressable.

The four different memory spaces are distinct

in the 8051 architecture, but are partly

overlapping in the

CC2430 to ease DMA

transfers and hardware debugger operation.

How the different memory spaces are mapped

onto the three physical memories (flash

program memory, 8 KB SRAM and hardware

registers) is described in sections 12.3.1 and

12.3.2.

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