CC2430-RTR1-F64Z datasheet(93/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 93 of 232

Table 38: DMA Configuration Data Structure

Byte

Offset

Bit

Name

Description

7:0

SRCADDR[15:8]

The DMA channel source address, high

7:0

SRCADDR[7:0]

The DMA channel source address, low

7:0

DESTADDR[15:8]

The DMA channel destination address, high. Note that flash memory is not directly

writeable.

7:0

DESTADDR[7:0]

The DMA channel destination address, low. Note that flash memory is not directly

writeable.

7:5

VLEN[2:0]

Variable length transfer mode. In word mode, bits 12:0 of the first word is considered

as the transfer length.

000/111

Use LEN for transfer count

001

Transfer the number of bytes/words specified by first byte/word + 1 (up

to a maximum specified by LEN). Thus transfer count excludes length

byte/word

010

Transfer the number of bytes/words specified by first byte/word (up to a

maximum specified by LEN). Thus transfer count includes length

byte/word.

011

Transfer the number of bytes/words specified by first byte/word + 2 (up

to a maximum specified by LEN).

100

Transfer the number of bytes/words specified by first byte/word + 3 (up

to a maximum specified by LEN).

101

reserved

110

reserved

4:0

LEN[12:8]

The DMA channel transfer count.

Used as maximum allowable length when VLEN = 000/111. The DMA channel

counts in words when in WORDSIZE mode, and in bytes otherwise.

7:0

LEN[7:0]

The DMA channel transfer count.

Used as maximum allowable length when VLEN = 000/111. The DMA channel

counts in words when in WORDSIZE mode, and in bytes otherwise.

WORDSIZE

Selects whether each DMA transfer shall be 8-bit (0) or 16-bit (1).

6:5

TMODE[1:0]

The DMA channel transfer mode:

00 : Single

01 : Block

10 : Repeated single

11 : Repeated block

4:0

TRIG[4:0]

Select DMA trigger to use

00000 : No trigger (writing to

DMAREQ is only trigger)

00001 : The previous DMA channel finished

00010 – 11111 : Selects one of the triggers shown in Table 37. The trigger is

selected in the order shown in the table.

7:6

SRCINC[1:0]

Source address increment mode (after each transfer):

00 : 0 bytes/words

01 : 1 bytes/words

10 : 2 bytes/words

11 : -1 bytes/words

5:4

DESTINC[1:0]

Destination address increment mode (after each transfer):

00 : 0 bytes/words

01 : 1 bytes/words

10 : 2 bytes/words

11 : -1 bytes/words

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