CC2430-RTR1-F64Z datasheet(99/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 99 of 232

0000h

FFFFh

OVFL

Figure 20: Free-running mode

13.3.4 Modulo Mode

When the timer operates in modulo mode the

16-bit counter starts at 0x0000 and increments

at each active clock edge. When the counter

reaches the terminal count value held in

registers T1CC0H:T1CC0L, the counter is

reset to 0x0000 and continues to increment.

The flag T1CTL.OVFIF is set when the

terminal count value is reached. An interrupt

request is generated if the corresponding

interrupt mask bit TIMIF.OVFIM is set. The

modulo mode can be used for applications

where a period other then 0xFFFF is required.

The counter operation is shown in Figure 21.

0000h

T1CC0

OVFL

Figure 21: Modulo mode

13.3.5 Up/down Mode

In the up/down timer mode, the counter

repeatedly starts from 0x0000 and counts up

until the value held in T1CC0H:T1CC0L is

reached and then the counter counts down

until 0x0000 is reached as shown in Figure 22.

This timer mode is used when symmetrical

output pulses are required with a period other

than

0xFFFF,

and

therefore

allows

implementation of centre-aligned PWM output

applications. The flag T1CTL.OVFIF is not set

when the terminal count value is reached in

the up/down mode.

Clearing the counter by writing to T1CNTL will

also reset the count direction to the count up

from 0x0000 mode.

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