CC2430-RTR1-F64Z datasheet(88/234 Pages) TI

88 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 88 of 232

The behavior of each of the five DMA channels

is configured with the following parameters:

Source address

. The first address from which

the DMA channel should read data.

Destination address

. The first address to

which the DMA channel should write the data

read from the source address. The user must

ensure that the destination is writable.

Transfer count

. The number of transfers to

perform before rearming or disarming the DMA

channel and alerting the CPU with an interrupt

request. The length can be defined in the

configuration or it can be defined as described

next as VLEN setting.

VLEN setting.

The DMA channel is capable of

variable length transfers using the first byte or

word to set the transfer length. When doing

this, various options regarding how to count

number of bytes to transfer are available.

Priority

. The priority of the DMA transfers for

the DMA channel in respect to the CPU and

other DMA channels and access ports.

Trigger event

. All DMA transfers are initiated

by so-called DMA trigger events. This trigger

either starts a DMA block transfer or a single

DMA transfer. In addition to the configured

trigger, a DMA channel can always be

triggered

setting

its

designated

DMAREQ.DMAREQx flag. The DMA trigger

sources are described in Table 37 on page 92.

Source and Destination Increment.

The

source and destination addresses can be

controlled to increment or decrement or not

change, in order to give good flexibility for

various types of transfers.

Transfer

mode.

The

transfer

mode

determines whether the transfer should be a

single transfer or a block transfer, or repeated

versions of these.

Byte or word transfers.

Determines whether

each DMA transfer should be 8-bit (byte) or

16-bit (word).

Interrupt Mask.

An interrupt request is

generated upon completion of the DMA

transfer. The interrupt mask bit controls if the

interrupt generation is enabled or disabled.

M8:

Decide whether to use seven or eight bits

of length byte for transfer length. Only

applicable when doing byte transfers.

A detailed description of all configuration

parameters are given in the following sections.

13.2.2.1 Source Address

The address in XDATA memory where the

DMA channel shall start to read data.

13.2.2.2 Destination Address

The first address to which the DMA channel

should write the data read from the source

address. The user must ensure that the

destination is writable.

13.2.2.3 Transfer Count

The number of bytes/words needed to be

transferred for the DMA transfer to be

complete. When the transfer count is reached,

the DMA controller rearms or disarms the DMA

channel and alerts the CPU with an interrupt

request. The transfer count can be defined in

the configuration or it can be defined as a

variable length described in the next section.

13.2.2.4 VLEN Setting

The DMA channel is capable of using the first

byte or word (for word, bits 12:0 are used) in

source data as the transfer length. This allows

variable length transfers. When using variable

length transfer, various options regarding how

to count number of bytes to transfer is given.

In any case, the transfer count (LEN) setting is

used as maximum transfer count. Note that the

M8 bit (see page 90) is only used when byte

size transfers are chosen.

Options which can be set with VLEN are the

following:

1. Transfer

number

bytes/words

commanded by first byte/word + 1

(transfers the length byte/word, and

then as many bytes/words as dictated

by length byte/word)

2. Transfer

number

bytes/words

commanded by first byte/word

3. Transfer

number

bytes/words

commanded by first byte/word + 2

(transfers the length byte/word, and

then as many bytes/words as dictated

by length byte/word + 1)

4. Transfer

number

bytes/words

commanded by first byte/word + 3

(transfers the length byte/word, and

then as many bytes/words as dictated

by length byte/word + 2)

Figure 18 shows the VLEN options.

CC2430-RTR1-F64Z 数据表(PDF) 88 Page - Texas Instruments

CC2430-RTR1-F64Z 数据表(HTML) 88 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CC2430-RTR1-F64Z 数据表(PDF) 88 Page - Texas Instruments

CC2430-RTR1-F64Z 数据表(HTML) 88 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载