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CC2430-RTR1-F64Z 数据表(PDF) 65 Page - Texas Instruments

部件名 CC2430-RTR1-F64Z
功能描述  A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM
PDF  234 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CC2430-RTR1-F64Z 数据表(HTML) 65 Page - Texas Instruments

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CC2430
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 65 of 232
Bit
Name
Description
Flash chip erase done
0 Chip erase in progress
7
chip_erase_done
1 Chip erase done
PCON idle
0 CPU is running
6
pcon_idle
1 CPU is idle (clock gated)
CPU halted
0 CPU running
5
cpu_halted
1 CPU halted
Power Mode 0
0 Power Mode 1-3 selected
4
power_mode_0
1 Power Mode 0 selected
Halt status. Returns cause of last CPU halt
0 CPU was halted by HALT debug command
3
halt_status
1 CPU was halted by software or hardware breakpoint
Debug locked. Returns value of DBGLOCK bit
0 Debug interface is not locked
2
debug_locked
1 Debug interface is locked
Oscillators stable. This bit represents the status of the
CLKCON.XSOC_STB and CLKCON.HFRC_STB register bits.
0 Oscillators not stable
1
oscillator_stable
1 Oscillators stable
Stack overflow. This bit indicates when the CPU writes to
DATA memory space at address 0xFF which is possibly a
stack overflow
0 No stack overflow
0
stack_overflow
1 Stack overflow
Table 35: Debug Status
12.9.7 Hardware Breakpoints
The debug command SET_HW_BRKPNT
is used to set a hardware breakpoint. The
CC2430 supports up to four hardware
breakpoints. When a hardware breakpoint
is enabled it will compare the CPU
address bus with the breakpoint.. When a
match occurs, the CPU is halted.
When issuing the SET_HW_BRKPNT, the
external host must supply three data bytes
that define the hardware breakpoint. The
hardware breakpoint itself consists of 18
bits while three bits are used for control
purposes. The format of the three data
bytes
for
the
SET_HW_BRKPNT
command is as follows.
The first data byte consists of the
following:
bits 7-5
: unused
bits 4-3
: breakpoint number; 0-3
bit 2
: 1=enable, 0=disable
bits 1-0
: Memory bank bits. Bits
17-16
of
hardware
breakpoint.
The second data byte consists of bits 15-8
of the hardware breakpoint.
The third data byte consists of bits 7-0 of
the hardware breakpoint.



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