Data Sheet

ADPA7009-2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. 0 | 6 of 24

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3, 5, 6, 7, 9, 10, 12, 14, 16, 17, 19, 21, 22, 24

GND

Ground. Connect to a ground plane that has low electrical and thermal

impedance. See Figure 3 for the interface schematic.

4

RFIN

RF Signal Input. The RFIN pin is AC-coupled and matched to 50 Ω. See

Figure 4 for the interface schematic.

8, 23

VGG1, VGG2

Negative Gate Bias Control. The gate voltage must be applied to VGGx.

Adjust the negative voltage on the VGGx pin to set the IDQ to the desired

level. See Figure 5 for the interface schematic.

11, 20

VDD1, VDD2

Drain Biases for the Amplifier. See Figure 6 for the interface schematic.

13

VDET

Detector Diode Used for Measuring the RF Output Power. Detection by

the VDET pin requires the application of a DC bias voltage through an

external series resistor. Used in combination with VREF, the difference

detector voltage, VREF − VDET, is a temperature-compensated DC voltage

proportional to the RF output power. See Figure 7 for the interface

schematic.

15

RFOUT

RF Signal Output. The RFOUT pin is AC-coupled and matched to 50 Ω. See

Figure 9 for the interface schematic.

18

VREF

Reference Diode Voltage. Use the VREF pin for temperature compensation

of the VDET RF output power measurements. Used in combination with

VDET, this voltage provides temperature compensation to the VDET RF

output power measurements. See Figure 8 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc

ground.