Data Sheet

ADPA7009-2

THEORY OF OPERATION

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Rev. 0 | 18 of 24

The ADPA7009-2 is a GaAs, pHEMT, medium power amplifier with

integrated decoupling components. Figure 65 shows a simplified

block diagram. The drain current is set by the negative voltage ap-

plied to the VGG1 pin. The drain bias voltage is applied through the

VDD1 pin. The gate and drain can alternatively be biased through

the VGG2 and VDD2 pins. Bias inductors and 0.1 μF and 100

pF decoupling capacitors are integrated. The ADPA7009-2 uses a

cascaded, 4-stage amplifier operating in quadrature between two

90° hybrids.

The input signal is divided evenly in two. Each path is amplified

through four independent gain stages. The amplified signals are

then combined at the output. This balanced amplifier approach

forms an amplifier with a combined gain of 17.5 dB and a PSAT

value of 28.5 dBm. The gate pins are internally connected and can

be biased from either north or south of the circuit.

A portion of the RF output signal is directionally coupled to a diode

for detection of the RF output power. When the diode is DC biased,

the diode rectifies the RF power and makes the RF power available

for measurement as a DC voltage at VDET. To allow temperature

compensation of VDET, an identical and symmetrically located

circuit, minus the coupled RF power, is available through VREF.

Taking the difference of VREF − VDET provides a temperature-com-

pensated signal that is proportional to the RF output (see Figure

65).

Figure 65. ADPA7009-2 Architecture