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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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FT800Q-R 数据表(PDF) 20 Page - Bridgetek Pte Ltd. |
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FT800Q-R 数据表(HTML) 20 Page - Bridgetek Pte Ltd. |
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20 / 46 page  Copyright © Bridgetek Pte Ltd 20 FT800 Embedded Video Engine Datasheet Version 1.4 Document No.: BRT_000039 Clearance No.: BRT#001 Font Index => 16 18 20 21 22 23 24 25 26 27 28 29 30 31 116 t 8 8 4 4 5 6 8 9 8 6 7 8 10 13 117 u 8 8 5 7 9 10 14 18 7 10 12 14 18 24 118 v 8 8 6 7 8 10 13 16 11 9 11 12 16 21 119 w 8 8 8 10 12 14 18 23 7 13 16 18 23 32 120 x 8 8 6 7 8 10 12 16 7 9 11 12 16 21 121 y 8 8 5 7 8 10 13 16 7 9 11 12 16 21 122 z 8 8 5 7 8 9 12 16 5 9 11 12 16 21 123 { 8 8 3 5 6 6 8 11 3 6 7 8 11 14 124 | 8 8 3 3 4 5 6 9 5 4 5 6 8 10 125 } 8 8 3 5 6 6 8 11 10 6 7 8 11 14 126 ~ 8 8 7 8 10 10 14 19 3 12 14 16 21 29 127 DEL 8 8 0 0 0 0 0 0 2 4 5 6 8 10 Table 4-8 ROM font ASCII character width in pixels 128 Ç 144 É 160 á 176 ░ 192 └ 208 ð 224 Ó 240 - 129 ü 145 æ 161 í 177 ▒ 193 ┴ 209 Ð 225 ß 241 ± 130 é 146 Æ 162 ó 178 ▓ 194 ┬ 210 Ê 226 Ô 242 ‗ 131 â 147 ô 163 ú 179 │ 195 ├ 211 Ë 227 Ò 243 ¾ 132 ä 148 ö 164 ñ 180 ┤ 196 ─ 212 È 228 õ 244 ¶ 133 à 149 ò 165 Ñ 181 Á 197 ┼ 213 ı 229 Õ 245 § 134 å 150 û 166 ª 182 Â 198 ã 214 Í 230 µ 246 ÷ 135 ç 151 ù 167 º 183 À 199 Ã 215 Î 231 þ 247 ¸ 136 ê 152 ÿ 168 ¿ 184 © 200 ╚ 216 Ï 232 Þ 248 ° 137 ë 153 Ö 169 ® 185 ╣ 201 ╔ 217 ┘ 233 Ú 249 ¨ 138 è 154 Ü 170 ¬ 186 ║ 202 ╩ 218 ┌ 234 Û 250 · 139 ï 155 ø 171 ½ 187 ╗ 203 ╦ 219 █ 235 Ù 251 ¹ 140 î 156 £ 172 ¼ 188 ╝ 204 ╠ 220 ▄ 236 ý 252 ³ 141 ì 157 Ø 173 ¡ 189 ¢ 205 ═ 221 ¦ 237 Ý 253 ² 142 Ä 158 × 174 « 190 ¥ 206 ╬ 222 Ì 238 ¯ 254 ■ 143 Å 159 ƒ 175 » 191 ┐ 207 ¤ 223 ▀ 239 ´ 255 nbsp Table 4-9 ROM font Extended ASCII characters Note 1: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters. Note 2: All fonts included in the FT800 ROM are widely available to the market-place for general usage. See section nine for specific copyright data and links to the corresponding license agreements. 4.4 Parallel RGB Interface The RGB parallel interface consists of 23 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 signals each for R, G and B. Several registers configure the LCD operation of these signals as follow: REG_PCLK is the PCLK divisor the default is 0, and disables the PCLK output. PCLK frequency = System Clock frequency / REG_PCLK PCLK_POL define the clock polarity, =0 for positive active clock edge, and 1 for negative clock edge. REG_CSPREAD controls the transition of RGB signals with respect to PCLK active clock edge. When REG_CSPREAD=0, R[7:2], G[7:2] and B[7:2] signals change following the active edge of PCLK. When |
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